Ð þíÐ88(˜fragment@0/__overlay__external-gmac0-clock fixed-clockúð€ 'gmac0_clkin:Gusb-host-vbus-regulator regulator-fixedO bÿÿÿÿgdefaultuusb_host_vbusŽLK@¦LK@¾ÿÿÿÿG vcc1v8-eth-regulator regulator-fixedO bÿÿÿÿgdefaultuÉÝ1v8_ethŽw@¦w@¾ÿÿÿÿvcc3v3-eth-regulator regulator-fixed bÿÿÿÿgdefaultuÉÝ3v3_ethŽ2Z ¦2Z ¾ÿÿÿÿGfragment@1ïÿÿÿÿ__overlay__öÿÿÿÿ…ÿÿÿÿ‚ ÿÿÿÿ„input*5rmii>gdefaultuÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿIokayfragment@2ïÿÿÿÿ__overlay__P_ethernet-phy@0 ethernet-phy-ieee802.3-c22koÿÿÿÿ€gdefaultu‹è›Ð ­ÿÿÿÿ¹Gfragment@3ïÿÿÿÿ__overlay__etherneteth-wake-intn-pinctrlÇÿÿÿÿGeth-phy-rstn-pinctrlÇÿÿÿÿGvcc1v8-eth-en-pinctrlÇÿÿÿÿGvcc3v3-eth-enn-pinctrlÇÿÿÿÿGusbusb-host-vbus-en-pinctrlÇÿÿÿÿGfragment@4ïÿÿÿÿ__overlay__ Õhigh-speedãÿÿÿÿ èusb2-phyIokayfragment@5ïÿÿÿÿ__overlay__> Iokay__fixups__7ò/fragment@0/__overlay__/usb-host-vbus-regulator:gpio:0=ø/fragment@0/__overlay__/usb-host-vbus-regulator:vin-supply:0×/fragment@0/__overlay__/vcc1v8-eth-regulator:gpio:0/fragment@0/__overlay__/vcc3v3-eth-regulator:gpio:0/fragment@2/__overlay__/ethernet-phy@0:interrupt-parent:0/fragment@2/__overlay__/ethernet-phy@0:reset-gpios:0t/fragment@0/__overlay__/vcc1v8-eth-regulator:vin-supply:0/fragment@0/__overlay__/vcc3v3-eth-regulator:vin-supply:0/fragment@1:target:0…/fragment@1/__overlay__:assigned-clocks:0/fragment@1/__overlay__:assigned-clocks:8/fragment@1/__overlay__:assigned-clock-parents:0$/fragment@1/__overlay__:pinctrl-0:0$'/fragment@1/__overlay__:pinctrl-0:4$6/fragment@1/__overlay__:pinctrl-0:8%B/fragment@1/__overlay__:pinctrl-0:12%P/fragment@1/__overlay__:pinctrl-0:16^/fragment@2:target:0d/fragment@3:target:0fl/fragment@3/__overlay__/ethernet/eth-wake-intn-pinctrl:rockchip,pins:12/fragment@3/__overlay__/ethernet/eth-phy-rstn-pinctrl:rockchip,pins:12/fragment@3/__overlay__/ethernet/vcc1v8-eth-en-pinctrl:rockchip,pins:12/fragment@3/__overlay__/ethernet/vcc3v3-eth-enn-pinctrl:rockchip,pins:12/fragment@3/__overlay__/usb/usb-host-vbus-en-pinctrl:rockchip,pins:12{/fragment@4:target:04Š/fragment@4/__overlay__:phys:0/fragment@5:target:0__local_fixups__fragment@0__overlay__usb-host-vbus-regulatoruvcc1v8-eth-regulatoruvcc3v3-eth-regulatorufragment@1__overlay__*>fragment@2__overlay__ethernet-phy@0ufragment@5__overlay__> target-pathcompatibleclock-frequencyclock-output-names#clock-cellsphandleenable-active-highgpiopinctrl-namespinctrl-0regulator-nameregulator-min-microvoltregulator-max-microvoltvin-supplyregulator-always-onregulator-boot-ontargetassigned-clocksassigned-clock-parentsclock_in_outphy-handlephy-modephy-supplystatus#address-cells#size-cellsreginterrupt-parentinterruptsreset-assert-usreset-deassert-usreset-gpioswakeup-sourcerockchip,pinsmaximum-speedphysphy-namesgpio1vcc5v_ingpio0vcc3v3_sysgmac0crugmac0_miimgmac0_clkinoutgmac0_rx_ergmac0_rx_bus2gmac0_tx_bus2mdio0pinctrlpcfg_pull_noneusb_host1_xhciusb2phy0_host